A clock and data recovery (CDR) circuit is an integral part of a modern data communication system. A CDR circuit is connected to and interfaces with a data signal line that carries incoming data. The CDR circuit performs the function of extracting the incoming data and clock information from the incoming data stream. This function is typically performed with an electronic control loop that detects the incoming data. Based on the data edge locations in time, the electronic control loop makes a determination of the instantaneous phase of the data.
The electronic control loop subsequently aligns the electronic control loop's own internal clock with the phase of the incoming data. This alignment allows the CDR circuit to sample the data in the middle of the bit period to ensure that a maximum signal-to-noise ratio is achieved. The aligned clock signal is also referred to as the recovered clock signal because it represents a clock signal that is synchronous with the recovered data.
There are two main architectures in the prior art that are used to construct a clock and data recovery (CDR) circuit. The primary difference between the two systems is the way the recovered clock signal is generated. A first CDR type system generates the recovered clock signal with a voltage controlled oscillator (VCO). The VCO based system is capable of generating the recovered clock signal at the same frequency as the data. In addition, the VCO based system can vary the recovered clock phase to match the phase of the data.
A second CDR type system uses a phase interpolator to vary the phase of a reference clock signal that is supplied to it from another on-chip block (typically, a phase-lock loop (PLL)) that produces a nominal clock frequency that matches the nominal frequency of the incoming data. The interpolator produces a new clock signal with an interpolated phase that is varied to match the phase of the incoming data. This clock signal is then used to sample the data in the middle of the bit period. The interpolated clock signal, in this case, is also referred to as a recovered clock signal. Even though this system (i.e., the interpolated phase system) uses a reference clock signal with a fixed frequency, it can still adjust the interpolated clock frequency to match the variation in frequency of the incoming data. The frequency shift is accomplished by continuously varying the phase of the interpolated clock signal to translate it into a frequency shift.
The electronic control loop uses a phase detector at its input to compare the phase of the incoming data to the phase of the internal clock signal. The phase detector determines whether the clock phase is early or late relative to the incoming data signal. The electronic control loop subsequently makes a decision to vary the phase of the internal clock signal in such a way as to eliminate the phase difference between the clock signal and the incoming data signal.
The data sampling is accomplished through the use of input comparators that are driven from one or more phases of the internal (i.e., recovered) clock signal. Under ideal conditions, these comparators sample each data bit in the middle of the bit period and make a determination whether the bit is zero or the bit is one and pass on the decision as the recovered data.
A clock and data recovery (CDR) circuit of the phase interpolation variety tracks an incoming data stream by continuously varying the phase of the internal (i.e., recovered) clock signal through phase interpolation. A system that uses a phase interpolator CDR circuit can be used to recover data with a bandwidth that is higher than the native capability of the process technology. For example, it is possible to use a phase interpolator CDR system to recover a data stream running at four Gigabits per second (4 Gb/s) while using a process technology that can not operate at frequencies higher than one Gigahertz per second (1 GHz/s).
In such a case, the data stream is broken down into several parts and each part is processed in parallel at a lower speed. More specifically, the number of input comparators can be increased and these comparators no longer need to sample every consecutive bit. In the example mentioned above, this means that the number of comparators must be increased from one comparator to four comparators. Each of the four comparators would sample the data at a rate of one Giga sample per second (1 Gsample/s). Therefore, each of the four comparators samples every fourth bit from the data stream. The output of the four comparators is subsequently combined in the correct order to reconstruct the data stream.
In practice a system that uses a phase interpolator CDR circuit acquires more than one sample per bit in order to determine the phase of a given bit. In fact, two samples per bit are required in order for the phase detector to make an early-or-late determination for each bit. Therefore, for a CDR circuit with an internal clock running at the same frequency as that of the data stream, two comparators are used to sample the data stream. The two comparators, in this case, are driven by two clock phases that are separated by one hundred eighty degrees (180°). This results in a sample taken in the middle of the bit period (the data sample) and a sample taken near the edge of the bit period (the edge sample) as shown in FIG. 1.
A CDR circuit that operates at the same rate as the data rate of the incoming data stream would need two input comparators, a first input comparator for sampling the data in the middle of the bit period, and a second input comparator for sampling the edge of the bit period. This type of sampling is called “full rate, double sampling.” A CDR circuit that operates at one half of the data rate of the incoming data stream would need four input comparators. This type of sampling trades off more circuitry (and corresponding area) for a relaxation in the speed requirement. This type of sampling is called “half rate, double sampling.”
Finally, as the incoming data bits are sampled, they are processed by digital control circuitry that looks for bit transitions and determines whether the clock is sampling too early or too late. This is accomplished by comparing three consecutive data-edge-data samples and looking for a data transition. If there is no data transition in the data bit, then the sample set does not produce phase information. Otherwise, the three samples are compared. If the edge sample is the same as the first data sample, then the sampling clock is early. This situation is illustrated in FIG. 2. On the other hand, if the edge sample is the same as the second data sample, then the clock is late. This situation is illustrated in FIG. 3.
These early and late decisions are accumulated and used to advance or retard the phase of the interpolated clock signal. This is accomplished by a Finite State Machine (FSM) block that controls the phase interpolator and sets the phase position of the recovered clock signal.
Various types of prior art systems exist that use the double sampling technique for each bit in order to recover the clock and data information. The data and edge samples are produced by a digital filter and are used to make phase advancement or retardation decisions. U.S. Pat. No. 6,002,279 issued on Dec. 14, 1999 to W. P. Evans et al. entitled “Clock Recovery Circuit” discloses a CDR architecture in which a digital filter is implemented as a divide-by-sixteen (16) block and a phase interpolator is driven by a bank of nonlinear digital-to-analog converters (DACs). The nonlinear DACs are needed to maintain an appropriate bias condition for the bipolar phase interpolator circuit.
U.S. Pat. No. 6,122,336 issued on Sep. 19, 2000 to M. B. Anderson entitled “Digital Clock Recovery Circuit With Phase Interpolation” discloses a CDR architecture that uses an all-CMOS implementation which does not require the use of nonlinear digital-to-analog converters (DACs). This design uses phase interpolators to generate a large number of fine increments in the recovered clock phase. This design then uses a phase selection unit to pick an appropriate phase used in sampling the data. This implementation requires the generation of a large number of phases for the phase selection unit to choose from.
This added complexity is addressed in United States Patent Application No. 2003/0002607 A1 published on Jan. 2, 2003 by S. R. Mooney et al. entitled “Clock Recovery Using Clock Phase Interpolator.” This system eliminates the phase selection unit with a fast phase interpolator with fine increment resolution. The system starts with a delay-lock loop (DLL) that generates four clock phases. These phases are then fed to a phase interpolator that generates the final, desired clock phase. The phase interpolator is driven by a control circuit that takes the output of the phase detector and converts it to a digital signal using an analog-to-digital converter (ADC). The need for an ADC adds to the complexity of the implementation.
This added complexity is addressed in a paper entitled “A 0.4-4 Gb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual Loop PLLs” by K.-Y. K. Chang et al. published in the IEEE Journal of Solid-State Circuits, Volume 38, No. 5, pp. 747-754, May 2003. This system uses binary phase detectors that determine whether the sampling clock is early or late. These binary signals can be fed directly into the control logic circuitry to make the determination whether the phase interpolator should advance or retard the phase of the sampling (i.e., recovered) clock signal.
From the discussion and the references cited above it is clear that a canonical form exists for phase interpolator-based clock and recovery circuits. In general the prior art circuits contain a phase locked loop (PLL) or a delay lock loop (DLL) to generate the initial clock phases, one or more phase interpolators that generate the recovered clock signal, two or more phase detectors that determine the relationship of the clock signal relative to the data signal, and mixed-signal or digital control circuitry that determines the appropriate clock phase and controls the phase interpolators.
A communication system typically has to meet a minimum bit error rate (BER) in order to be useful. This means that the measurement of the bit error rate is one of the most fundamental measurements to be performed on a communication system. One of the most influential factors on the measurement of a bit error rate is the selection of the moment during which the clock and data recovery circuit samples the incoming data. Typically the clock and data recovery circuit searches for the center of a bit period and samples the data at that location.
The center of the bit period is the optimum location for the measurement because the data is expected to have the least amount of voltage noise and timing jitter at that location. In fact, if the clock and data recovery circuit is unable to locate the middle of the bit period and is erroneously sampling near the edge of the bit period, then bit errors will occur.
A typical high speed communication system is capable of transferring data at a rate of two and one half Gigabits per second (2.5 Gb/s) and might require a bit error rate of 10−12. This means that the communication system has to transfer at least 1012 bits without any bit errors. To conduct a bit error test in which 1012 bits are passed would require approximately six (6) minutes and forty (40) seconds. This length of test time is unacceptable for modern integrated circuit chips because conducting such a lengthy test would significantly increase the cost of manufacture of each chip. Reducing the time required for the bit error test can realize significant savings in the manufacturing cost of each chip.
Therefore, there is a need in the art for a system and method for providing a clock and data recovery circuit that has a fast bit error rate self test capability. There is also a need in the art for a system and method for minimizing the test time for testing a bit error rate in a clock and data recovery circuit.